Category: NI

Before installing the NI 1483. you must install the application software and device driver. Install the

software in the following order:

1.LabVIEW—Refer to the LabVIEW Release Notes for installation instructions for LabVIEW

and system requirements for the LabVIEW software. Refer to the LabVIEW Upgrade Notes for

additional information about upgrading to the most recent version of LabVIEW for Windows.

Documentation for LabVIEW is available by selecting Start»All Programs»National

Instruments»LabVIEW»LabVIEW Manuals.

2.LabVIEW FPGA Module—Refer to the LabVIEW FPGA Module Release and Upgrade Notes

for installation instructions and information about getting started with the LabVIEW FPGA

Module.

Documentation for the LabVIEW FPGA Module is available by selecting Start»All Programs»

National Instruments»LabVIEW»LabVIEW Manuals.

3.NI-RIO—Refer to the NI-RIO Readme on the NI-RIO installation media for system requirements

and installation instructions for the NI-RIO driver.

Documentation for the NI-RIO driver software is available by selecting Start»All Programs»

National Instruments»NI-RIO.

4.NI-IMAQ—Refer to the NI Vision Acquisition Software Release Notes on the NI Vision

Acquisition Software installation media for system requirements and installation instructions for

the NI-IMAQ driver.

Documentation for the NI-IMAQ driver software is available by selecting Start»All Programs»

National Instruments»Vision»Documentation»NI-IMAQ.

5.(Optional) NI Vision Development Module—Refer to the NI Vision Development Module

Readme on the NI Vision Development Module installation media for system requirements and

installation instructions.

Documentation for the NI Vision Development Module is available by selecting Start»All

Programs»National Instruments»Vision»Documentation»NI Vision.

The NI 1483R is an image acquisition device that supports Base, Medium, Full, and Extended Full

(80-bit) configuration Camera Link-compatible cameras. The NI 1483R is comprised of an

NIFlexRIOTM FPGA module and an NI FlexRIO adapter module (NI 1483). This document explains

how to install and configure the NI 1483R, how to acquire images using a LabVIEW FPGA example

VI, and lists the specifications for the NI 1483.

Required Components

The following items are necessary to set up and use the NI 1483R:

❑ NI FlexRIO adapter module (NI 1483)

❑ NI FlexRIO FPGA module

❑ The following software packages:

– LabVIEW 2010 or later

– LabVIEW FPGA Module 2010 or later

– NI-RIO 4.0 or later driver software

– NI-IMAQ 4.6.1 or later driver software, included with NI Vision Acquisition Software

– (Optional) NI Vision Development Module 2010 or later for creating machine vision

applications

❑ One of the following system considerations:

– PXI/CompactPCI or PXI Express/CompactPCI Express chassis with a PXI/CompactPCI or a

PXI Express/CompactPCI Express embedded controller

– MXI kit and a PC running Windows 7/Vista/XP/2000

❑ Cables for connecting a Camera Link-compatible camera to the NI 1483. Refer to the Connectivity

Options section for a list of applicable cables and accessories.

The NI 5791 can upconvert and downconvert RF signals ranging from 200 MHz to 4.4 GHz.

This document contains signal information and lists the specifications of the NI 5791R, which

is composed of the NI FlexRIO FPGA module and the NI 5791. This document also contains

tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI

and how to create and run your own LabVIEW project with the NI 5791R.

Note NI 5791R refers to the combination of your NI 5791 adapter module and

your NI FlexRIO FPGA module. NI 5791 refers to your NI 5791 adapter module

only.

Note The NI 5791 is only compatible with the NI PXIe-796xR FPGA modules.

Note Before configuring your NI 5791. you must install the appropriate software

and hardware. Refer to the NI FlexRIO FPGA Module Installation Guide and

Specifications for installation instructions.

Note For EMC compliance, operate this device according to the documentation.

Key Features

The NI 5791 includes the following key features:

R…F.. .f..r.e..q..u..e..n..c.y.. .r..a.n..g..e……………………………………….200 MHz to 4.4 GHz

.I.n..s.t..a.n..t.a..n..e..o..u..s. .b..a..n..d..w…i.d..t.h………………………………..100 MHz

.A..D…C…………………………………………………………….14-bit dual channel at 130 MS/s

.D..A…C…………………………………………………………….16-bit dual channel at 130 MS/s, interpolated

to 520 MS/s

P…h..a.s..e.. .n..o..i.s..e………………………………………………….<94 dBc/Hz, 10 kHz offset, 2.4 GHz carrier

D…y..n..a..m…i.c.. .r.a..n..g..e……………………………………………..>105 dB

.N..o..i..s.e.. .f.i.g..u..r..e…………………………………………………<8 dB at 2 GHz

.E..V…M…………………………………………………………….<1.5% (RMS)

.R..e..c..e.i..v..e. .(..R..X…).. .I.P..3………………………………………….+1 dBm at 2 GHz

T…r.a..n..s..m…i.t. .(.T…X…). .I.P..3…………………………………………+17 dBm at 2 GHz

The NI 5791 is an RF transceiver adapter module designed to work in conjunction with your

NI FlexRIO™ FPGA module. The NI 5791 features the following connectors and chips:

• 2-channel, 130 MS/s analog-to-digital converter (ADC) with 14-bit accuracy

• 2-channel, 130 MS/s (520 MS/s after interpolation) digital-to-analog converter (DAC)

with 16-bit accuracy

• LO input and LO output connectors to support LO sharing for multiple-channel applications

• Timing chip with clocking options from the backplane and the front panel

• Programmable attenuators

• Selectable receive and transmit filters

• The following front panel connectors:

– RX IN

– LO OUT

– CLK IN

– CLK OUT

– LO IN

– TX OUT

Overview

The National Instruments VXIpc-870B Series embedded controllers

are flexible, high-performance Pentium III-based controllers in a

rugged package ideal for VXI systems. An NI VXIpc-870B Series

controller in a VXI chassis gives you direct control of VXI registers,

memory, interrupts, and triggers while maintaining compatibility

with the scores of software packages and tools available for general

market desktop PC computers.

The NI VXIpc-870B Series controllers come in four models with

various options that provide the most cost-effective VXI embedded

control solution available. Table 1 details the standard features of the

VXIpc-870B Series controllers. The VXIpc-870B Series controllers

require two VXI C-size slots. The VXIpc-871B and VXIpc-874B

include all the standard features, but also add an integrated 24X max

CD-ROM drive. The VXIpc-872B and VXIpc-875B also contain all

standard features, but instead of a CD-ROM drive,they offer one PCI

expansion slot.

If you require a solid-state storage medium for operation in harsh

environments,you can use the VXIpc-870B Series controllers with an

internal solid-state flash drive in place of the internal hard drive, or a

removable solid-state flash drive that you can install and remove

directly from the front panel.

NI VXIpc-870B Series

• VXIplug&play compliant

• VXIpc-871B,VXIpc-872B

• 1.26 GHz Pentium III processor

• VXIpc-874B,VXIpc-875B

• 1.4 GHz Pentium III processor

• Intel 815E chipset

• High-performance

PCI-based peripherals

• 10/100BaseT Ethernet

• Wide Ultra2 SCSI

• CardBus controller for PCMCIA

(16-bit) and CardBus (32-bit)2

• GPIB

• NI MITE-based VXIbus interface

• DMA

• VME64

• Storage and memory

• 256 MB, upgradeable to 512 MB

• Internal 1.44 MB floppy drive

• Internal hard drive, 30 GB minimum1

• Programmable NI watchdog timer

• Complete VXI Slot 0 resource manager

• Jumperless configuration

NI-VXI/NI-VISA Software

• Windows 2000/XP/NT

• VxWorks

• Linux 2.2/2.4 kernel

1Minimum drive size does not apply to solid state flash drive options.

Because of rapidly changing hard drive technology, please contact

National Instruments for the latest hard drive options.

The A/D FIFO generates a signal that indicates when it contains

conversion data. You can read the signal state from the PC-LPM-16PnP

Status Register 1.

The output from the ADC is in two’s complement format. In unipolar

input mode (0 to 10 V or 0 to 5 V input range configuration), the data

from the ADC is interpreted as a 12-bit positive number ranging from 0

to 4,095. In bipolar input mode (±5 or± 2.5 V input range configuration), 

the data from the ADC is interpreted as a two’s

complement number ranging from -2,048 to +2047. The ADC’s output

is always sign-extended to 16 bits by board circuitry so that data values

read from the FIFO are 16 bits wide.

The ADC on the PC-LPM-16PnP includes calibration circuitry that

makes it possible to minimize zero, full-scale, and linearity errors. The

ADC goes through a self-calibration cycle under software control. To

properly use this ADC auto-calibration feature, you need an accurate

input stage that does not introduce significant offset and gain errors.

The analog input stage on the PC-LPM-16PnP maintains the required

accuracy without trimpot adjustments.

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, a jumperselectable

gain stage, and a 12-bit sampling ADC. The 12-bit output is

sign-extended to 16 bits before it is stored in a 256-word deep FIFO memory.

The input multiplexer stage is made up of a CMOS analog input

multiplexer and has 16 analog input channels (channels 0 through 15).

With the input multiplexer stage, input overvoltage protection of

±45 V is available powered on, or ±35 V powered off.

The PC-LPM-16PnP uses a successive-approximation analog-to-digital

converter (ADC). Software-selectable gains of 0.5, 1, and 2 for the

input signal combined with the ADC’s fixed input range of

±5 V yield four useful analog input signal ranges, 0 to 10 V,

±5 V, 0 to 5 V, and ±2.5 V.

When an A/D conversion is complete, the ADC clocks the result into

the A/D FIFO. The A/D FIFO is 16 bits wide and 256 words deep. This

FIFO serves as a buffer to the ADC and has two benefits. First, any time

an A/D conversion is complete, the A/D FIFO saves the value for later

reading, and the ADC can start a new conversion. Secondly, the A/D

FIFO can collect up to 256 A/D conversion values before losing any

information, thus giving the software some extra time (256 times the

sample interval) to catch up with the hardware. If the A/D FIFO stores

more than 256 values without the A/D FIFO being read, an error

condition called A/D FIFO Overflow occurs and A/D conversion

information is lost.

The interrupt control circuitry routes any enabled interrupts to the

selected interrupt request line. The PC-LPM-16PnP has six interrupt

request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9.

The PC-LPM-16PnP generates interrupts in three different situations:

• When an A/D conversion generates data that can be read from FIFO

• When an active low-level signal is detected on the EXTINT* line

• When a rising-edge signal is detected on counter 2 output

The PC-LPM-16PnP individually enables and clears each one of these

interrupts. For more detailed information on generating interrupts

externally, see the EXTINTEN bit of the Command Register 1

description in Appendix D, Register-Level Programming.

Analog Input and Data Acquisition Circuitry

The PC-LPM-16PnP has 16 channels of analog input with 12-bit

A/D conversion. Using the timing circuitry, the PC-LPM-16PnP can

also automatically time multiple A/D conversions. Figure 3-3 shows a

block diagram of the analog input and data acquisition circuitry.

The ADC on the PC-LPM-16PnP includes calibration circuitry that

makes it possible to minimize zero, full-scale, and linearity errors.

Functional Overview

The following are the major components making up the

PC-LPM-16PnP:

• PC I/O channel interface circuitry

• Analog input and data acquisition circuitry

• Digital I/O circuitry

• Timing I/O circuitry

You can execute data acquisition functions by using the analog input

circuitry and some of the timing I/O circuitry. The internal data and

control buses interconnect the components. The theory of operation for

each of these components is explained in the remainder of this chapter.

The block diagram in Figure 3-1 shows a functional overview of the

PC-LPM-16PnP.

The circuitry consists of Plug and Play address decoders, data buffers,

I/O channel interface timing control circuitry, and interrupt control

circuitry. The circuitry monitors address lines SA4 through SA15 to

generate the board enable signal, and uses lines SA0 through SA3 plus

timing signals to generate the onboard register select signals and

read/write signals. The data buffers control the direction of data transfer

on the bidirectional data lines based on whether the transfer is a read or

write operation.