Functional Overview

The following are the major components making up the

PC-LPM-16PnP:

• PC I/O channel interface circuitry

• Analog input and data acquisition circuitry

• Digital I/O circuitry

• Timing I/O circuitry

You can execute data acquisition functions by using the analog input

circuitry and some of the timing I/O circuitry. The internal data and

control buses interconnect the components. The theory of operation for

each of these components is explained in the remainder of this chapter.

The block diagram in Figure 3-1 shows a functional overview of the

PC-LPM-16PnP.

The circuitry consists of Plug and Play address decoders, data buffers,

I/O channel interface timing control circuitry, and interrupt control

circuitry. The circuitry monitors address lines SA4 through SA15 to

generate the board enable signal, and uses lines SA0 through SA3 plus

timing signals to generate the onboard register select signals and

read/write signals. The data buffers control the direction of data transfer

on the bidirectional data lines based on whether the transfer is a read or

write operation.