Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, a jumperselectable

gain stage, and a 12-bit sampling ADC. The 12-bit output is

sign-extended to 16 bits before it is stored in a 256-word deep FIFO memory.

The input multiplexer stage is made up of a CMOS analog input

multiplexer and has 16 analog input channels (channels 0 through 15).

With the input multiplexer stage, input overvoltage protection of

±45 V is available powered on, or ±35 V powered off.

The PC-LPM-16PnP uses a successive-approximation analog-to-digital

converter (ADC). Software-selectable gains of 0.5, 1, and 2 for the

input signal combined with the ADC’s fixed input range of

±5 V yield four useful analog input signal ranges, 0 to 10 V,

±5 V, 0 to 5 V, and ±2.5 V.

When an A/D conversion is complete, the ADC clocks the result into

the A/D FIFO. The A/D FIFO is 16 bits wide and 256 words deep. This

FIFO serves as a buffer to the ADC and has two benefits. First, any time

an A/D conversion is complete, the A/D FIFO saves the value for later

reading, and the ADC can start a new conversion. Secondly, the A/D

FIFO can collect up to 256 A/D conversion values before losing any

information, thus giving the software some extra time (256 times the

sample interval) to catch up with the hardware. If the A/D FIFO stores

more than 256 values without the A/D FIFO being read, an error

condition called A/D FIFO Overflow occurs and A/D conversion

information is lost.