Month: July 2025

The A/D FIFO generates a signal that indicates when it contains

conversion data. You can read the signal state from the PC-LPM-16PnP

Status Register 1.

The output from the ADC is in two’s complement format. In unipolar

input mode (0 to 10 V or 0 to 5 V input range configuration), the data

from the ADC is interpreted as a 12-bit positive number ranging from 0

to 4,095. In bipolar input mode (±5 or± 2.5 V input range configuration), 

the data from the ADC is interpreted as a two’s

complement number ranging from -2,048 to +2047. The ADC’s output

is always sign-extended to 16 bits by board circuitry so that data values

read from the FIFO are 16 bits wide.

The ADC on the PC-LPM-16PnP includes calibration circuitry that

makes it possible to minimize zero, full-scale, and linearity errors. The

ADC goes through a self-calibration cycle under software control. To

properly use this ADC auto-calibration feature, you need an accurate

input stage that does not introduce significant offset and gain errors.

The analog input stage on the PC-LPM-16PnP maintains the required

accuracy without trimpot adjustments.

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, a jumperselectable

gain stage, and a 12-bit sampling ADC. The 12-bit output is

sign-extended to 16 bits before it is stored in a 256-word deep FIFO memory.

The input multiplexer stage is made up of a CMOS analog input

multiplexer and has 16 analog input channels (channels 0 through 15).

With the input multiplexer stage, input overvoltage protection of

±45 V is available powered on, or ±35 V powered off.

The PC-LPM-16PnP uses a successive-approximation analog-to-digital

converter (ADC). Software-selectable gains of 0.5, 1, and 2 for the

input signal combined with the ADC’s fixed input range of

±5 V yield four useful analog input signal ranges, 0 to 10 V,

±5 V, 0 to 5 V, and ±2.5 V.

When an A/D conversion is complete, the ADC clocks the result into

the A/D FIFO. The A/D FIFO is 16 bits wide and 256 words deep. This

FIFO serves as a buffer to the ADC and has two benefits. First, any time

an A/D conversion is complete, the A/D FIFO saves the value for later

reading, and the ADC can start a new conversion. Secondly, the A/D

FIFO can collect up to 256 A/D conversion values before losing any

information, thus giving the software some extra time (256 times the

sample interval) to catch up with the hardware. If the A/D FIFO stores

more than 256 values without the A/D FIFO being read, an error

condition called A/D FIFO Overflow occurs and A/D conversion

information is lost.

The interrupt control circuitry routes any enabled interrupts to the

selected interrupt request line. The PC-LPM-16PnP has six interrupt

request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9.

The PC-LPM-16PnP generates interrupts in three different situations:

• When an A/D conversion generates data that can be read from FIFO

• When an active low-level signal is detected on the EXTINT* line

• When a rising-edge signal is detected on counter 2 output

The PC-LPM-16PnP individually enables and clears each one of these

interrupts. For more detailed information on generating interrupts

externally, see the EXTINTEN bit of the Command Register 1

description in Appendix D, Register-Level Programming.

Analog Input and Data Acquisition Circuitry

The PC-LPM-16PnP has 16 channels of analog input with 12-bit

A/D conversion. Using the timing circuitry, the PC-LPM-16PnP can

also automatically time multiple A/D conversions. Figure 3-3 shows a

block diagram of the analog input and data acquisition circuitry.

The ADC on the PC-LPM-16PnP includes calibration circuitry that

makes it possible to minimize zero, full-scale, and linearity errors.

Functional Overview

The following are the major components making up the

PC-LPM-16PnP:

• PC I/O channel interface circuitry

• Analog input and data acquisition circuitry

• Digital I/O circuitry

• Timing I/O circuitry

You can execute data acquisition functions by using the analog input

circuitry and some of the timing I/O circuitry. The internal data and

control buses interconnect the components. The theory of operation for

each of these components is explained in the remainder of this chapter.

The block diagram in Figure 3-1 shows a functional overview of the

PC-LPM-16PnP.

The circuitry consists of Plug and Play address decoders, data buffers,

I/O channel interface timing control circuitry, and interrupt control

circuitry. The circuitry monitors address lines SA4 through SA15 to

generate the board enable signal, and uses lines SA0 through SA3 plus

timing signals to generate the onboard register select signals and

read/write signals. The data buffers control the direction of data transfer

on the bidirectional data lines based on whether the transfer is a read or

write operation.

There are different ways to assign the base address to your board:

• For Windows 95, the base address and interrupt should be set

automatically. However, if you want to view or change these

settings, you can set the board resources using the Device

Manager. Windows 95 will automatically allocate resources, but

these can be changed in the Device Manager:

a. Click the right mouse button on My Computer to bring up system properties.

b. Select Device Manager.

c. Select Data Acquisition Devices.

d. Select the PC-LPM-16.

You can change address and interrupt settings on the Resources page.

• For Windows 3.10 or 3.11, you can use the NI-DAQ Configuration

Utility (formerly WDAQCONF) to assign the board resources. If a

standard configuration utility is present in the system, you will not

be able to modify the board resources.

• You can use a standard configuration utility like Intel ISA

Configuration Utility (ICU). ICU dynamically assigns the base

address to your board when you boot up the computer. You can also

lock the board resources when you use ICU. For additional

information on ICU, contact Intel Corporation for a copy of Plug

and Play Specification version 1.0a.

Non-Plug and Play

To configure the non-Plug and Play PC-LPM-16 board, refer to

Appendix C, Using Your PC-LPM-16 (Non-PnP) Board.

Board Configuration

Plug and Play

The PC-LPM-16PnP is fully compatible with the industry-standard

Intel/Microsoft Plug and Play Specification version 1.0a. A Plug and

Play system arbitrates and assigns resources through software, freeing

you from manually setting switches and jumpers. These resources

include the board base I/O address and interrupt channels. Each

PC-LPM-16PnP is configured at the factory to request these resources

from the Plug and Play Configuration Manager.

The Configuration Manager receives all of the resource requests at

startup, compares the available resources to those requested, and

assigns the available resources as efficiently as possible to the Plug and

Play boards. Application software can query the Configuration

Manager to determine the resources assigned to each board without

your involvement. The Plug and Play software is installed as a device

driver or as an integral component of the computer BIOS.

Base I/O Address and Interrupt Selection

You can configure your PC-LPM-16PnP to use base addresses in the

range of 100 to FFF0 hex. The PC-LPM-16PnP occupies 16 bytes of

address space and must be located on a 16-byte boundary. Therefore,

valid addresses include 100, 110, 120…, FFE0, FFF0 hex. This

selection is software-configured and does not require you to manually

change any settings on the board.

The PC-LPM-16PnP can use interrupt channels 3, 4, 5, 6, 7, and 9.

Software Installation

If you are using NI-DAQ, refer to your NI-DAQ release notes to install

your driver software. Find the installation section for your operating

system and follow the instructions given there.

If you are using LabVIEW, refer to your LabVIEW release notes to

install your application software. After you have installed LabVIEW,

refer to the NI-DAQ release notes and follow the instructions given

there for your operating system and LabVIEW.

If you are using LabWindows/CVI, refer to your LabWindows/CVI

release notes to install your application software. After you have

installed LabWindows/CVI, refer to the NI-DAQ release notes and

follow the instructions given there for your operating system and

LabWindows/CVI.

If you are a register-level programmer, refer to Appendix D, Register-

Level Programming, for software configuration information.

Hardware Installation

You can install the PC-LPM-16PnP in any available expansion slot in

your computer. The following are general installation instructions, but

consult your computer user manual or technical reference manual for

specific instructions and warnings.

1. Turn off and unplug your computer.

2. Remove the top cover or access port to the I/O channel.

3. Remove the expansion slot cover on the back panel of the computer.

4. Insert the PC-LPM-16PnP board into any 8-bit or 16-bit slot. It may

be a tight fit, but do not force the board into place.

5. Screw the mounting bracket of the PC-LPM-16PnP board to the

back panel rail of the computer.

6. Replace the cover.

7. Plug in and turn on your computer.

The PC-LPM-16PnP is installed.